1. Field of the Invention
The present invention relates to a method of forming a pattern of a two-layer metal film, and more particularly, it relates to a method of forming a second metal film on a first metal film pattern provided on the major surface of a semiconductor substrate.
2. Description of the Prior Art
In an electrode or interconnection layer formed on a semiconductor substrate of a semiconductor device, the material for a part being in contact with the semiconductor substrate is restricted in response to treatment of the semiconductor substrate, while the material for another part may be selected in response to the characteristic of the semiconductor device. In other words, required is patterning of a two-layer metal film formed by dissimilar metals. With reference to FIGS. 1A to 1F, description is now made on a conventional method of forming the pattern of such a two-layer metal film.
First, a heat resistant first metal film 2 is deposited entirely over the major surface of a semiconductor substrate 1 as shown in FIG. 1A. The first metal film 2 must be resistant against heat since the semiconductor substrate 1 is subjected to heat treatment in a later step. The deposited first metal film 2 is subjected to photolithography and reactive ion etching (RIE) etc., to provide a first metal film pattern 3 of a prescribed configuration as shown in FIG. 1B. Then the first metal film pattern 3 is utilized as a mask to introduce impurity into prescribed positions on both sides thereof through ion implantation, and the semiconductor substrate 1 is subjected to heat treatment to diffuse the impurity, thereby to form an impurity region 4 as shown in FIG. 1C. After the heat treatment, a resist film 5 is formed entirely over the major surface of the semiconductor substrate 1 including the first metal film pattern 3. An opening 6 is formed in the resist film 5 through photolithography, to expose the upper surface of the first metal film pattern 3. Then, as shown in FIG. 1E, a second metal film 7 is formed entirely over the resist film 5 including the exposed first metal film pattern 3. The second metal film 7 is selected in view of its functional characteristic, dissimilarly to the first metal film 2. Finally the resist film 5 and the second metal film 7 provided on the resist film 5 are removed through a lift-off method to provide a two-layer metal film pattern of a prescribed configuration, which two-layer metal film pattern consists of the first metal film pattern 3 being in contact with the semiconductor substrate 1 and a second metal film pattern 8 formed thereon, as shown in FIG. 1F.
In such a conventional pattern forming method, extremely accurate alignment is required for the photolithography for forming the opening 6 in the resist film 5. In a semiconductor device refined with higher density of integration, however, it is extremely difficult to correctly expose the resist film 5 on the fine first metal film pattern 3 in view of exposure accuracy. Thus, it has been almost impossible to form the second metal film 8 in high accuracy on the fine first metal film pattern 3.
On the other hand, a method of forming a fine gate electrode is disclosed in "Self-Aligned Pt-Buried Gate FET process with Surface Planarization Technique for GaAs LSI" Terada et al.), IEEE GaAs IC Symposium, 1983, pp. 138-141. In this method, an SiO.sub.2 layer to be employed as a dummy in pattern formation of the gate electrode is deposited entirely over the major surface of a semiconductor substrate and a cap metal is patterned thereon in a prescribed configuration. The patterned cap metal is utilized as a mask to remove the exposed portion of the SiO.sub.2 layer by etching, thereby to provide an SiO.sub.2 layer of a prescribed configuration. A resist film is coated entirely over the major surface of the semiconductor substrate including the SiO.sub.2 layer, and thereafter the surface of the resist film is etched to expose the upper surface of the SiO.sub.2 layer. The exposed SiO.sub.2 layer is removed by a plasma etching method to define an opening in the resist film, thereby to form a gate electrode in the opening through a lift-off method.
A similar method of forming a fine gate electrode is disclosed in "A New Self-Align Technology for Low Noise GaAs MESFET's-Sidewall-Assisted Pattern Inversion Technology-" (Hagio et al.) in IEDM Technical Digest, 1984, pp. 194-197.
However, the disclosure in the aforementioned literature is not directed to a method of forming a pattern of a two-layer metal film as in the present invention, but relates to a method of forming a pattern of a single-layer metal film. Further, since the gate electrode is formed by evaporating a metal film in the opening of the resist film formed by utilizing the dummy gate of the SiO.sub.2 film, the contact surface between the gate electrode and the major surface of the semiconductor substrate is not stable. In addition, the size of the opening in the resist film is varied with exposure accuracy of the upper surface of the dummy gate, to influence size accuracy of the gate electrode.
Thus, the aforementioned prior art examples have none of advantages obtained by the present invention upon application to formation of a gate electrode, such as stable contact between a previously formed first metal film pattern and the major surface of a semiconductor substrate, assurance of width of the first metal film pattern serving as a lower layer of the gate electrode in high accuracy.